The candidate will function in an FPGA developer/verification role working in a cross functional team environment to design verify and test modem/signal processing-based FPGA firmware for radio communication systems.
Successful candidates must have experience with RTL development using VHDL as well as FPGA verification methodologies using System Verilog.
Candidate will be required to analyze requirements create FPGA specifications/development plans create FPGA verification/test plans code firmware designs in VHDL code test benches in System Verilog and verify designs meet requirements.
Work Schedule : 9/80; 9 out of every 14 days totaling 80 hours Every other Friday off
Qualifications:
Location Rochester NY
Base Salary $110000 $140000
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